Field of the Invention
The present invention relates to a metal oxide semiconductor field effect transistor, and more particularly to a method of making a metal oxide semiconductor field effect transistor with a lightly doped drain structure capable of reducing a threshold voltage and a junction capacitance, and simultaneously simplifying a manufacturing process. According to a general metal oxide semiconductor field effect transistor (MOSFET) with a lightly doped drain (LDD) structure, hot carriers are generated due to a high electric field formed at edge portions of its gate electrode. In a case that the generated hot carriers are trapped in a gate insulating film, a defect is generated in the gate insulating film, thereby causing the operation characteristic of the MOSFET to be deteriorated and the life time of the MOSFET to be shortened.
So as to reduce the hot carrier effect, a MOSFET with a LDD structure such as FIG. 1C has been suggested.
On a P type semiconductor substrate 11, first, field oxide films 12 are formed to isolate adjacent cells from one another, as shown in FIG. 1A. Thereafter, a gate insulating film 13 is formed over the entire surface of P type semiconductor substrate 11 including the field oxide films 12. On the gate insulating film 13, a gate electrode 14 having a certain width is formed within each active region.
The exposed surface of gate electrode 14 is subjected to an oxidization, thereby forming a gate cap oxide film 15.
Over the entire exposed surface, a polysilicon layer 16 with a certain thickness is formed to provide gate side walls. Subsequently, the polysilicon layer 16 is subjected to an anisotropic etching using a reactive ion etching (RIE) method, thereby forming gate side walls 17 at sidewalls of the gate electrode 14, respectively, as shown in FIG. 1B.
At this time, the gate cap oxide film 15 formed on the surface of gate electrode 14 serves as an etch stopper.
By using the gate cap oxide film 15 and gate sidewalls 17 as a mask, N.sup.+ type (namely, high concentration) impurity ions are then implanted in a portion of the surface of P type semiconductor substrate 11 corresponding to the active region. According to a diffusion of the impurity ions, N.sup.+ type source and drain regions 18a, 18b are formed in the active region between the field oxide films 12 and gate sidewalls 17. Thereafter, the gate sidewalls 17 are removed, as shown in FIG. 1C.
By performing a self-alignment with the gate cap oxide film 15 as a mask, N.sup.- type (namely, low concentration) impurity ions are then implanted in a portion of the surface of P type semiconductor substrate 11 corresponding to the active region. According to a diffusion of the impurity ions N.sup.- type source and drain regions 19 and 19a are formed in the active region between the gate cap oxide film 15 and the N.sup.+ type source and drain regions 18a and 18b. Accordingly, the source and drain regions of MOSFET form a LDD structure comprising low and high concentration impurity regions.
According to the LDD structure of MOSFET shown in FIG. 1C, a hot carrier effect due to a high electric field can be reduced. Since the source and drain regions comprise N.sup.31 type impurity regions and N.sup.+ type impurity regions, however, a resistance is increased, thereby causing the slow operation speed.
In addition, it is impossible to obtain source and drain regions having desired accurate widths, due to the difficulty of accurately controlling the thickness of the gate sidewalls. Consequently, a short channel is caused.
So as to reduce the short channel effect, P type impurity ions should be doped with a high concentration in P type semiconductor substrate. As a method for obtaining P type high concentration substrate, P type impurity ions are overall implanted with a high concentration in P type semiconductor substrate. As another method, P type impurity ions are partly implanted in P type substrate to additionally form P type impurity regions enclosing N.sup.- type source/drain regions and N.sup.+ type source/drain regions.
The short channel effect of MOSFET with a LDD structure can be reduced by the above two methods.
However, a threshold voltage of MOSFET and a junction capacitance of source/drain regions are increased in proportion to a doping concentration of an impurity.
Since a MOSFET with a LDD structure according to the above methods has a semiconductor substrate having a higher concentration, as compared with a conventional MOSFET with a LDD structure, the threshold voltage and the junction capacitance are increased, thereby causing the characteristic of MOSFET in operation to be deteriorated.
FIG. 2A to FIG. 2F show manufacturing sectional views of a MOSFET with a LDD structure which is capable of reducing the short channel effect and the junction capacitance of source/drain regions.
Referring to FIG. 2A, field oxide films 22 are formed on P type substrate 21 by performing a conventional local oxidation of silicon (LOCOS) process to define field regions and active regions.
As shown in FIG. 2B, a gate oxide film 23, a first polysilicon film 24, a nitride film and a second polysilicon film 26 are formed in this order and then the second polysilicon film 26, the nitride film, the first polysilicon film 24 and the gate oxide film are patterned in this order so as to form a gate with a triple structure.
Thereafter, an oxide film is formed on the whole surface of P type substrate 21 and then the oxide film is anisotopically etched with a RIE method to form side wall oxide films 27. As shown in FIG. 2C, a third polysilicon film 28 doped with N.sup.+ type impurity is formed on the whole surface of P type substrate 21.
Thereafter, the third polysilicon film 28 is selectively etched such that it is merely remained in the active region between the field oxide films 22.
Over the whole surface of P type substrate 21, a photoresist film 29 is coated and then the photoresist film 29 is etched back until the surface of the third polysilicon film 28 is exposed.
As shown in FIG. 2D, the second polysilicon 26 and the third polysilicon film 28 are etched until the surface of the nitride film 25 formed on the gate electrode 24 is exposed.
At this time, the second polysilicon 26 and the third polysilicon 28 formed on the gate electrode 24 are all removed, thereby there remains only the third polysilicon film 28 doped with N.sup.+ type impurity on the active region between the gate electrode 24 and the field oxide films 22.
At this time, the remaining third polysilicon film 28 doped with N.sup.+ type impurity serves as a diffusion source for forming N.sup.+ type source/drain regions, upon performing the following impurity diffusion process for forming source/drain regions. The nitride film 25 exposed on the gate electrode 24 serves as an etch stopper, upon the performance of the above etching process.
As shown in FIG. 2E, the photoresist film 29 and the side wall oxide film 27 are removed in this order.
By using the gate electrode (24) and the remaining polysilicon film (28) as a mask, N.sup.- type (low concentration) impurity ions and P.sup.- type impurity ions are then implanted.
According to a diffusion of the N.sup.31 type impurity ions and the P.sup.- type impurity ions, N.sup.- type source and drain regions 18a and 18b are formed.
At this time, N.sup.+ type impurity ions are also diffused from the polysilicon film 28 doped with N.sup.+ type impurity ions, thereby N.sup.+ type (high concentration) source and drain regions 30a and 30b are formed. simultaneously, P.sup.- type impurity ions are also diffused, thereby forming P.sup.- type (low concentration ) impurity regions 32a and 32b.
In the above ion-implantation process, since N.sup.- type impurity ions and P.sup.- type impurity ions are implanted using the third polysilicon film 28 and the gate electrode 24 in which N.sup.- type impurity ions and P.sup.- type impurity ions are remained, as a mask, N.sup.+ type source and drain regions 31a and 32b are formed such that they are contacted with N.sup.+ type source and drain regions 30a and 30b, respectively, and P.sup.- type (low concentration) impurity regions 32a and 32b are formed such that N.sup.- type source and drain regions 31a and 31b are merely enclosed by them, respectively.
As shown in FIG. 2F, a SOG film 33 for planarization is formed over the whole surface of P.sup.+ type substrate 21. The SOG film 33 is subjected to an etching process to form a contact for inter-connecting source/drain regions with the third polysilicon 28. Thereafter, a metal electrode 34 is finally formed.
Since P.sup.- type impurity regions are formed such that they merely enclose N.sup.- type source and drain regions, as shown in FIG. 2F, the MOSFET with a LDD structure shown in FIG. 2F has an advantage capable of more reducing a junction capacitance and a threshold voltage, as compared with a conventional MOSFET with a LDD structure in which P.sup.- type impurity regions enclose all of N.sup.- type (low concentration) source and drain regions and N.sup.+ type (high concentration) source and drain regions. However, the MOSFET has a disadvantage, in that many processes such as the formation processes and the etching precesses of the first polysilicon film, the second polysilicon film and the nitride film are required, to form the gate with a triple structure.
The MOSFET also has another disadvantage, in that many manufacturing processes such as the deposition process and the etching process of the third polysilicon film which is used as a diffusion source to form high concentration source and drain regions and simultaneously is used for an inter connection of source and drain metal electrodes with source and drain impurity regions, coating of photoresist and etching-back should be all performed. Consequently, the conventional MOSFET with a LDD structure shown in FIG. 2F has a problem, in that the manufacturing process thereof becomes complicating.